In reply to leya:
I would use realtime and $realtime.
In my SVA Handbook I recommend the use of specific notations as they provide information about the use of the object. Am providing those guideline http://systemverilog.us/vf/notation_sv.pdf
You may disagree with my notation, and that is OK. Choose a notation that you feel comfortable with, but be consistent.
property p_clk_freq;
realtime current_time;
@ (posedge clk)
disable iff ( !(!(reset) && (flag)))
('1, current_time = $realtime) |=>
(clock_input <= ($realtime - (current_time-0.001ns))|| ($time - (current_time+0.001ns)));
endproperty
ap_clk_freq: assert property (clk_freq);
// Old code on clock frequency check I wrote
property p_clk_hi;
realtime v;
@(posedge clk) (1, v=$realtime) |-> @(negedge clk) ($realtime-v)==300ns;
endproperty
ap_clk_hi: assert property(p_clk_hi);
property p_clk_lo;
realtime v;
@(negedge clk) (1, v=$time) |-> @(posedge clk) ($realtime-v)==700ns;
endproperty
ap_clk_lo: assert property(p_clk_lo);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
See Paper: 1) VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf