Clock Frequency check is passing in logs , but in waveforms assertion is failing

SystemVerilog
,
1

Hi ,

I have written below 2 different codes to check the frequency of clock (100Mhz) , I can see there is no error in the logs is printed but waveform is showing fail at every posedge of clock , Please help me in understanding where i’m making mistake :

1 . First way
module debug_clk_assertions(
input dbg_clk,
input nSRST
);

timeunit 1ns;
timeprecision 100ps;
bit debug_clk_assertion_enable = 1’b0;

realtime clk_period =1000.0/100.0ns; // =10ns

property debug_sys_clk_frequency_check ;
realtime current_time;
@(posedge dbg_clk)
disable iff (!nSRST)
('1, current_time = $realtime) |=> ((clk_period <= $realtime - (current_time - 0.1ns)) && (clk_period >= $realtime - (current_time + 0.1ns)) );
endproperty

dbg_sys_clk_frequency_check: assert property (debug_sys_clk_frequency_check)
$display(“TB_INFO : clk correct”);
else
$error(“TB_INFO : clk not correct clk_period=%d”,clk_period);
endmodule

2 : Second code
module debug_clk_assertions(
input dbg_clk,
input nSRST
);

timeunit 1ns;
timeprecision 100ps;
bit debug_clk_assertion_enable = 1’b0;

realtime clk_period =1000.0/100.0ns; // =10ns
property p_clk_freq3;
realtime current_time;
@ (posedge clk)
disable iff ( !(!(reset) && (flag)))
('1, current_time = $realtime) |=> (1, $display (“p=%t”, $realtime - current_time))
##0 (($realtime - current_time) <= clk_period + 1ns && // logical and
($realtime - current_time) >= clk_period - 1ns);
endproperty
dbg_sys_clk_frequency_check: assert property (debug_sys_clk_frequency_check)
$display(“TB_INFO : clk correct”);
else
$error(“TB_INFO : clk not correct clk_period=%d”,clk_period);
endmodule

Help is appreciated

2

In reply to ashivani:
Your code look ok:


property debug_sys_clk_frequency_check ;
    realtime current_time;
    @(posedge dbg_clk)
     disable iff (!nSRST)
     ('1, current_time = $realtime) |=>
     ((clk_period <= $realtime - (current_time - 0.1ns)) && (clk_period >= $realtime - (current_time + 0.1ns)) );
  endproperty
3

In reply to ben@SystemVerilog.us:

In reply to ashivani:
Your code look ok:


property debug_sys_clk_frequency_check ;
realtime current_time;
@(posedge dbg_clk)
disable iff (!nSRST)
('1, current_time = $realtime) |=>
((clk_period <= $realtime - (current_time - 0.1ns)) && (clk_period >= $realtime - (current_time + 0.1ns)) );
endproperty

Hi Ben , still the assertion is failing in the waveforms , is any connection or anything i’m missing out here ?

4

In reply to ashivani:

run an example on edaplaygrund and show it to me.
Ben