Clock Frequency check is passing in logs , but in waveforms assertion is failing

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

In reply to ashivani:
Your code look ok:


property debug_sys_clk_frequency_check ;
realtime current_time;
@(posedge dbg_clk)
disable iff (!nSRST)
('1, current_time = $realtime) |=>
((clk_period <= $realtime - (current_time - 0.1ns)) && (clk_period >= $realtime - (current_time + 0.1ns)) );
endproperty

Hi Ben , still the assertion is failing in the waveforms , is any connection or anything i’m missing out here ?