Class inside a package

SystemVerilog
,
7

In reply to Ramyas:

You’ve nested package declarations. Follow this:

package bus_agent;

`include "file1.sv"
`include "stim.sv"

  // stim.sv does an include of pkgA.sv
  // So a pre-processor ends up with:
  package A; // Syntax error

HTH
Srini
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