CAN I use class handle and/or get it using uvm_config_db inside the module.I am just trying to access data items of a class.But it is giving compilation error :The following is the code :-
module check_50;
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "mc_cgm_ral_sample.sv"
int tn_expected=0 ;
int tp_expected=0 ;
int tn_actual=0;
int tp_actual=0;
int cnt_actual =0;
//bit update_stat=0;
bit checker_on=0;
bit checker_off=0;
bit upd0_stat;
bit h_cycle_done ;
bit cnt_ap;
bit cnt_an;
bit cnt_ep;
bit cnt_en;
int t_on_actual;
int t_on_exp_value;
int t_off_exp_value;
int div_value_mux0;
int div_value_mux1;
int div_value_mux2;
int div_value_mux3;
int div_value_mux4;
int div_value_mux5;
bit checking_at_first=1;
int delay;
bit [255:0]divider_exists;
clk_if clk_if;
ral_block_MC_CGM regmodel;
initial
begin
// if(!uvm_config_db#(virtual clk_if)::get(this,"","clk_if",clk_if))
// `uvm_error("NOVIF","clk_if is unset")
if (!uvm_config_db#(ral_block_MC_CGM)::get(this,"","regmodel",regmodel))
`uvm_error("NOregmodel","regmodel is unset")
end
fork ////continously looking for the transitions in upd status register
//////////////////////top_thread1
forever
begin
//upd0_stat = regmodel.MC_CGM_MUX_0_DIV_UPD_STAT.get();
regmodel.MC_CGM_MUX_0_DIV_UPD_STAT.read(status ,upd0_stat);
// $display("upd0_stat = %b and time =%0t" ,upd0_stat,$time);
@(posedge sif.ipg_clk);
end
forever
@(posedge sif.ipg_clk)
if(sif.ips_addr == 'h320 && sif.ips_module_en ==1 ) ///getting the values////divider0
begin
div_value_mux0 = regmodel.MC_CGM_MUX_0_DC_6.DIV.get();
end
//////////////////////top_thread2
forever
begin
// @(posedge sif.ipg_clk);
begin
@(negedge upd0_stat )
begin
checker_on = 1; //////upd_stat transition from 1-> 0 has occured now apply the logic
checker_off =0;
cnt_ap=0;
cnt_an=0;
cnt_en=0;
cnt_ep=0;
h_cycle_done=0;
$display("Divider configuration has been changed ,upd0_stat = %b and time =%0t and checker_on=%d" ,upd0_stat,$time,checker_on);
end
end
while(checker_on == 1 && checker_off == 0 )
begin
// @(posedge sif.ipg_clk)
fork
begin
////////subthread0
begin
while(h_cycle_done==0 && cnt_ap==0) //collect posedge of ref. clk after upd_stat transition
begin
@(posedge vif.o_clk_mux[0])
tp_actual =$time;
$display("tp_actual =%d " ,tp_actual);
cnt_ap=1;
end
end
//////////subthread2
begin
while(h_cycle_done==0 && cnt_an==0) //collect negedge of ref. clk after upd_stat transition
begin
@(negedge vif.o_clk_mux[0])
tn_actual =$time;
$display("tn_actual =%d " ,tn_actual);
cnt_an=1;
end
end
///////////subthread3
begin
while(h_cycle_done==0 && cnt_ep==0) //collect posedge of divided clk after upd_stat transition
begin
@(posedge vif.o_clk_mux_div6[0])
tp_expected =$time ;
$display("tp_expected =%d " ,tp_expected);
cnt_ep=1;
end
end
////////////subthread4
begin
while(h_cycle_done==0 && cnt_en==0) //collect negedge of divided clk after upd_stat transition
begin
@(negedge vif.o_clk_mux_div6[0])
tn_expected =$time ;
$display("tn_expected =%d " ,tn_expected);
cnt_en=1;
end
end
///////////subthread5
begin
wait(cnt_ap==1 && cnt_an==1 && cnt_ep==1 && cnt_en==1 && h_cycle_done==0 ) ////ALL EDGES COLLECTED
begin
if(tn_actual>tp_actual)
begin
t_on_actual=tn_actual -tp_actual;
end
else
begin
t_on_actual=tp_actual -tn_actual;
end
if(tn_expected > tp_expected )
begin
t_on_exp_value = tn_expected -tp_expected;
end
else
begin
t_off_exp_value = tp_expected -tn_expected;
end
if(tn_expected > tp_expected ) //CHECKING AT NEGEDGE OF DIVIDED CLOCK
begin
if(t_on_exp_value == (div_value_mux0+1)*t_on_actual )
begin
cnt_ap=0;
cnt_an=0;
cnt_ep=0;
// cnt_en=0; //commented to store neg_edge
end
else
begin
$display("fail ,t_on_actual=%d,t_on_exp_value=%d, div_value_mux0=%d and the time is %0t",t_on_actual,t_on_exp_value,div_value_mux0,$time); `uvm_error("compare","MISMATCH in divider output and reference clock");
cnt_ap=0;
cnt_an=0;
cnt_ep=0;
// cnt_en=0; //commented to store negedge
end
end
else //CHECKING AT POSEDGE OF DIVIDED CLOCK
begin
if(t_off_exp_value == (div_value_mux0+1)*t_on_actual )
begin
cnt_ap=0;
cnt_an=0;
// cnt_ep=0; //commented to store posedge
cnt_en=0;
end
else
begin
cnt_ap=0;
cnt_an=0;
// cnt_ep=0; //commented to store posedge
// checking_at_first=1;
cnt_en=0;
end
end
end
end
end
////////partial thread(independent of above loop looking for the next upd
begin
wait(upd0_stat ==1) ////continuously checking for the next update////if goes high then block the current
begin
checker_on =0;
checker_off = 1; //////upd_stat transition from 1-> 0 has occured now apply the logic
h_cycle_done=1;
$display("upd0_stat = %b and time =%0t and checker_off=%d" ,upd0_stat,$time,checker_off);
end
end
join_any//////////////////////////////end of fork 1
end
end //////////////////////////end of thread 2
join///////////////////////end of fork 2
endmodule
The compilation error I am getting is expecting keyword endmodule at at the line where fork statement starts. I dont know the exact issue which is preventing it from compilation.