Checking clock period using system verilog assertion

In reply to jaecho@broadcom:

Could you tell me what the antecedent part ( (('1,current_time=$realtime) ) means?
(('1,current_time=$realtime) |=>(clk_period==$realtime-current_time));

The ('1,current_time=$realtime) is called a sequence_match_item

sequence_expr ::=  // one of the possibilities is   
( sequence_expr {, sequence_match_item }) [ sequence_abbrev ]

sequence_match_item ::=
    operator_assignment
  | inc_or_dec_expression
  | subroutine_call

sequence_abbrev ::= consecutive_repetition
consecutive_repetition ::=
  [* const_or_range_expression ]
  | [*]
  | [+] 

In this case, ('1,current_time=$realtime) the '1 is a sequence expression, which means that at every attempt, it will succeed. sequence_match_item are typically used in things like


property p; // if wr, data -> mem, check data is properly written after 4 cycles 
  int v_data, v_addr;   // this is a slow memory, or it goes through other paths. 
  (wr, v_data=data, v_addr=addr) |-> ##4 mem[v_addr]==mem_data;
endproperty 

Ben Cohen SystemVerilog.us