Checking clock period using system verilog assertion

SystemVerilog
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6

In reply to raghav kumar:

I have a question. I’m still learning SVA, and I have not seen the following syntax used in the above example.
Could you tell me what the antecedent part ( (('1,current_time=$realtime) ) means? Thank you.

(('1,current_time=$realtime) |=>(clk_period==$realtime-current_time));