Checking clock period using system verilog assertion

SystemVerilog
,
19

In reply to silverace99:

Hi I know this is an old thread, but I’m quite interested in the OP’s assertion code as I’m trying to write clock assertions as well. I have two questions:

  1. In the property, the OP has written this:
(('1,current_time=$realtime) |=>(clk_period==$realtime-current_time));

What is the '1 at the beginning of the statement for? What does it achieve?

The 1’b1 (a more typical application here) makes the antecedent true, and thus variable in the sequence match item is updated. You can replace the 1’b1 with a variable (e.g., k), but if that variable evaluates to zero, the property is vacuous.

  1. Let’s say I want to pull out the value of $realtime-current_time into an error message if this property catches a failure. Is there a way I can pull out the value of a variable inside a property? If not, what are my options?

Two solutions: Edit code - EDA Playground


module M;
  bit clk; 
  realtime t1, clk_period=20.0;
  initial forever #11 clk=!clk; 

  property p2;
   realtime current_time;
   @(posedge clk)
    ('1,current_time=$realtime) |=>
    (clk_period==$realtime-current_time);
  endproperty
  ap2: assert property(p2) else 
     begin 
       $display ("error"); // local variable is not accessible here ******!!!
     end  
    
 
    function automatic bit check_period(realtime now_time); 
      if ($realtime-now_time != clk_period) begin 
        t1=$realtime-now_time; // <<<<module variable update here
        return 0;
      end 
      else return 1'b1;   
    endfunction : check_period
    
   property p3;
     realtime current_time;
     bit pass;
     @(posedge clk)
      ('1,current_time=$realtime) |=>
     (1, pass=check_period(current_time));
  endproperty
    ap3: assert property(p3);  
 endmodule

Another option is to use tasks and do whatever you want. See my recently published paper

Abstract: Understanding the engine behind SVA provides not only a better appreciation and limitations of SVA, but in some situations provide features that cannot be simply implemented with the current definition of SVA. This paper first explains, by example, how a relatively simple assertion example can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multithreading and exit of threads upon a condition, such as an error in the assertion. The paper then provides examples that uses computational variables within threads; those variables can cause, in some cases, errors in SVA. The strictly emulation model with tasks solves this issue.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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