Checking clock period using system verilog assertion

SystemVerilog
,
18

Hi I know this is an old thread, but I’m quite interested in the OP’s assertion code as I’m trying to write clock assertions as well. I have two questions:

  1. In the property, the OP has written this:
(('1,current_time=$realtime) |=>(clk_period==$realtime-current_time));

What is the '1 at the beginning of the statement for? What does it achieve?

  1. Let’s say I want to pull out the value of $realtime-current_time into an error message if this property catches a failure. Is there a way I can pull out the value of a variable inside a property? If not, what are my options?

Thanks!