Checking clock period using system verilog assertion

SystemVerilog
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11

In reply to SAKET@ KUMAR:

You CAN use real in expressions that result in a Boolean. For example

property preal; 
    	real v; 
    	(a, v=3.14) |=> v> 4.0; 
    endproperty 
    ap_real: assert property(@(posedge clk) preal  );

You cannot use real in clock delays or repeat time.


// ILLEGAL
    a ##1.2 b