Check the value of `define macro

SystemVerilog
8

In reply to kpkrishna:

`define TEST 5
class  A;
  rand int x;
  function void post_randomize();
     if (`TEST  == 32'd45)
     begin
      `define TEST1
       $display("TEST 1 DEFINE");
     end
     else
     begin
      `define TEST0
      ;
     end
     `ifdef TEST1
        $display("TEST 1 DEFINED ");
     `else
       KKKKKKKKKKKKKKKK
     `endif
  endfunction
endclass
module test;
 A a = new();
 initial
 begin
  a.randomize();
 end
endmodule

Can you help me in finding the issue here. Since TEST define value is 5 , i should get compilation error. But i am not getting