Change in bits between requests constraint

SystemVerilog
,
1

I need to write a constraint to check where an 8 bit request signal only changed 3 of those 8 bits between any two consecutive requests.

Is there a way to write a constraint for this without having to save previous request value, xor it with current value, etc?

Thanks

2

In reply to UVM_learner6:

  class req;
     rand bit[7:0] data;
     constraint toggle_bits {$countones(data ^ const'(data)) == 3; }
  endclass
3

In reply to dave_59:

In reply to UVM_learner6:

  class req;
rand bit[7:0] data;
constraint toggle_bits {$countones(data ^ const'(data)) == 3; }
endclass

Thanks Dave for the solution. I tried to understand what casting to “const” means and found this from one of your replies to another user. Could you kindly break this down into simpler terms for me? What does “the type of the expression to be cast shall pass through unchanged” mean? Does it mean this is internally equivalent to saving the “previous data” and doing an XOR?

–
Section 6.24.1 Cast operator says

1800-2012 LRM wrote:
An expression may be changed to a constant with a const cast.
const’(x)

When casting an expression as a constant, the type of the expression to be cast shall pass through unchanged.
The only effect is to treat the value as though it had been used to define a const variable of the type of the expression

Thank you!

4

In reply to UVM_learner6:

It just means the type of expression inside the cast is self-determined. Normally when you have c = (a + b), all of the operands get extended to the width of the largest operand before performing the addition.

If you had

bit a = 1;
bit [1:0] b = 2;
bit [2:0] c;

c = a + b; // c would be 3'b4
c = const'(a + b); // c would be 3'b0
// same as
begin 
   automatic const bit [1:0] ab = (a + b);
   c = ab;
end
5

In reply to dave_59:

In reply to UVM_learner6:

  class req;
rand bit[7:0] data;
constraint toggle_bits {$countones(data ^ const'(data)) == 3; }
endclass

Thanks Dave, when I try using const I get this error :

System verilog keyword ‘const’ is not expected to be used in this context.

Any idea why this happens? If I replace it with a constant number, it works. The casting seems to be the problem.

Thanks.

6

In reply to UVM_learner6:

It likely a tool issue. Please contact your tool vendor.