Change in bits between requests constraint

SystemVerilog
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5

In reply to dave_59:

In reply to UVM_learner6:

  class req;
rand bit[7:0] data;
constraint toggle_bits {$countones(data ^ const'(data)) == 3; }
endclass

Thanks Dave, when I try using const I get this error :

System verilog keyword ‘const’ is not expected to be used in this context.

Any idea why this happens? If I replace it with a constant number, it works. The casting seems to be the problem.

Thanks.