Case statement in SV

SystemVerilog
,
1

Hi,
I have a case statement like


case(argument_from_command_line)
  ALL_A : data = 32'hAAAA_AAAA;
  ALL_5 : data = 32'h5555_5555;
  ALL_1 : data = 32'hFFFF_FFFF;
  RAND  : data = $urandom();
  INCR  : data = data+1;
endcase

So my question is that if I pass argument_from_command_line with the specific pattern then I will get that pattern for all the test(regression) but what I want is if I don’t pass an argument from the command line then it should take any case for multiple call of this case statement.

2

In reply to J_M:

$value$plusargs() returns zero if no matching argument was found. You can use that as a flag to randomize your argument.

3

In reply to dave_59:
Hi Dave,

Thanks for the reply I am doing somewhat you suggested

What I am doing right now is,


string data_pattern_arr[] = {"ALL_5","ALL_A","ALL_1","RAND","INCR"};
data_pattern_arr.shuffle();

// If I dont pass any argument from command line then I will assign this array to it

argument_from_cammand_line = data_pattern_arr[($urandom_range(1,5))];

So I just want to ask that is there any inbuild SV function to do that?

4

In reply to J_M:

If you call

$value$plusargs("TEST=%s", argument_from_cammand_line);

It leaves argument_from_cammand_line unmodified if there is no +TEST argument on the command line.

Also there is no need to do both the shuffle and the $urandom_range&mdashyou are randomizing twice.