Case statement in SV

SystemVerilog
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3

In reply to dave_59:
Hi Dave,

Thanks for the reply I am doing somewhat you suggested

What I am doing right now is,


string data_pattern_arr[] = {"ALL_5","ALL_A","ALL_1","RAND","INCR"};
data_pattern_arr.shuffle();

// If I dont pass any argument from command line then I will assign this array to it

argument_from_cammand_line = data_pattern_arr[($urandom_range(1,5))];

So I just want to ask that is there any inbuild SV function to do that?