Capture data only on rising falling signal

SystemVerilog
,
1

Hi
In the test program below, I want the TestClass to capture data only on clk 0 to 1 and 1 to 0 transition.
But it actually captures the data on other clk transitions such as 0 to z and z to 0 too.
How can I modify the TestClass for my purpose?

interface MyIf();
  logic clk = 0;
  logic [7:0] dt = '0;
endinterface

class TestClass;
  logic [7:0] q[$];
  virtual MyIf vif;

  task store_data_and_print();
    for (int i = 0; i < 4; i++) begin
      @(posedge vif.clk or negedge vif.clk) q.push_back(vif.dt);
    end

    foreach (q[i]) begin
      $display("%d", q[i]);
    end
  endtask
endclass

module test;
  MyIf myIf();
  TestClass testClass;

  initial begin
    $dumpfile("dump.vcd"); $dumpvars;
    testClass = new();
    testClass.vif = myIf;

    fork
      testClass.store_data_and_print();
      begin
        #1 myIf.dt = 1; #1 myIf.clk = ~myIf.clk;  // To capture
        #1 myIf.dt = 2; #1 myIf.clk = ~myIf.clk;  // To capture
        #1 myIf.dt = 10;#1 myIf.clk = 1'bz;       // Not to capture 
        #1 myIf.dt = 11;#1 myIf.clk = 0;          // Not to capture
        #1 myIf.dt = 3; #1 myIf.clk = 1;          // To capture
        #1 myIf.dt = 4; #1 myIf.clk = 1;          // To capture
      end
    join
  end
endmodule

Result:
1
2
10
11

Thanks

2

In reply to trg:

Why is your clock declared as logic, not bit?

You can use a do-while loop

  for (int i = 0; i < 4; i++) begin
      do begin
        wait(!$isunknown(vif.clk));
        @(vif.clk);
      end while ($isunknown(vif.clk));
      q.push_back(vif.dt);
    end

P.S. your last line needs clk = 0, not 1 to capture

3

In reply to dave_59:

Your code worked for me. Thanks.
I used logic instead of bit because in my actual environment they are bi-directional signals similar to DDR-DRAM interface’s DQ and DQS.