Capture data only on rising falling signal

SystemVerilog
,
2

In reply to trg:

Why is your clock declared as logic, not bit?

You can use a do-while loop

  for (int i = 0; i < 4; i++) begin
      do begin
        wait(!$isunknown(vif.clk));
        @(vif.clk);
      end while ($isunknown(vif.clk));
      q.push_back(vif.dt);
    end

P.S. your last line needs clk = 0, not 1 to capture