I like to run an example ‘hello_world’ of the package uvm-1.2 in Questa -64 10.7d.
Unfortunately, it doesn’t work out of the box.
vlog hello_world.sv
QuestaSim-64 vlog 10.7d Compiler 2019.02 Feb 15 2019
Start time: 09:15:08 on Jul 21,2023
vlog -reportprogress 300 hello_world.sv
– Compiling module hello_world
– Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
** Note: (vlog-2286) hello_world.sv(26): Using implicit +incdir+/tools/modelsim/10.7d/questasim/uvm-1.1d/…/verilog_src/uvm-1.1d/src from import uvm_pkg
Top level modules:
hello_world
End time: 09:15:10 on Jul 21,2023, Elapsed time: 0:00:02
Errors: 0, Warnings: 0
vsim hello_world
vsim hello_world
Start time: 09:15:29 on Jul 21,2023
** Note: (vsim-3812) Design is being optimized…
** Error (suppressible): producer.sv(58): (vopt-7063) Failed to find ‘get_tr_stream’ in hierarchical name ‘get_tr_stream’.
Region: hello_world.producer.
** Error (suppressible): producer.sv(58): (vopt-7063) Failed to find ‘get_tr_stream’ in hierarchical name ‘get_tr_stream’.
Region: hello_world.producer.
Optimization failed
Error loading design
End time: 09:15:30 on Jul 21,2023, Elapsed time: 0:00:01
Errors: 2, Warnings: 0
Would you let me know what I did wrong? - Thanks!