I like to run an example ‘hello_world’ of the package uvm-1.2 in Questa -64 10.7d. Unfortunately, it doesn’t work out of the box. vlog hello_world.sv QuestaSim-64 vlog 10.7d Compiler 2019.02 Feb 15 2019 Start time: 09:15:08 on Jul 21,2023 vlog -reportprogress 300 hello_world.sv – Compiling module…

In reply to XuanTran : Just I tried this example. It is working fine in my environment. Maybe your environment/setup is not complete.

In reply to chr_sue : Thanks for your quick response. Do you have any idea what’s missing in my setup environment? I am new to UVM.

In reply to XuanTran : I have this code put to EDAPlayground. See here [image] EDA Playground Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

In reply to chr_sue : Thanks for spending time on this issue. I found the problem. By default, my machine uses uvm-1.1d to build files. ** Note: (vlog-2286) hello_world.sv(26): Using implicit +incdir+/tools/modelsim/2023.2/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg I used …

Can't run an example 'hello_world' with Questa 10.7d

UVM

chr_sue July 21, 2023, 5:57pm 4

In reply to XuanTran:

I have this code put to EDAPlayground.
See here