In reply to meeteedesai:
SystemVerilog does not make it easy to connect different interface instances together. You have to connect each signal individually. The simplest approach is putting the signals you want to connect in the port list of the interface
interface channel(inout txdata, rxdata);
wire data;
endinterface
module host(channel p);
// drive p.txdata
// read p.rxdata
endmodule
module device(channel p);
// drive p.txdata
// read p.rxdata
endmodule
module top;
wire line1, line2;
channel h(.txdata(line1), .rxdata(line2));
channel d(.rxdata(line1), .txdata(line2));
host u1(h);
device u2(d);
endmodule
Another option is using a single interface with modport expressions
interface channel;
logic line1,line2;
wire data;
modport h(output .txdata(line1), input .rxdata(line2));
modport d(input .rxdata(line1), output .txdata(line2));
endinterface
module host(channel.h p);
// drive p.txdata
// read p.rxdata
endmodule
module device(channel.d p);
// drive p.txdata
// read p.rxdata
endmodule
module top;
channel c();
host u1(c);
device u2(c);
endmodule