Can you use 2 different instances of same interface to connect with each other in top module?

SystemVerilog
,
2

In reply to meeteedesai:


interface my_if;
  bit [ 7 : 0 ] txdata;
  bit [ 7 : 0 ] rxdata;
endinterface


module top;
  my_if foo();
  my_if bar();

  assign foo.txdata = bar.rxdata;
endmodule

You’re probably looking for something else, but this matches your stated requirements.
Regards,
Mark