Can we use $display in property assertions

SystemVerilog
, ,
1
  • I am trying to use display statement in the assertion property, as shown below, but I am getting an error as follows

Errors
Error-[SE] Syntax error
Following verilog source has syntax error :
“/vobs/asic_adc_dac_testchip/hydra_t/SE/assertions/hydra_t_strobe_assertions.sv”,
89: token is ‘$display’, column 84
(1, current_time = $time) |=> @(ev_data_delay) ($time - current_time)
$display("\t setup_hold_checker= %d ",($time - current_time) ) >
(SETUP_TIME+HOLD_TIME);

property setup_hold_checker;
    time current_time;
    @(posedge (clk ^ CK_EDGE_SEL))
      disable iff (~resetn || disable_assertion)	
      (1, current_time = $time) |=> @(ev_data_delay) ($time - current_time) $display("\t **setup_hold_checker**= %d ",($time - current_time) ) > (SETUP_TIME+HOLD_TIME); 
      
         
  endproperty: setup_hold_checker
2

In reply to venkatasubbarao:

You can, but you have a syntax error. Need a comma ‘,’ before the $display. After you fix that, you have another functional problem.

3

In reply to dave_59:

yes sir you are right i got following error i had tried that before as well ending up with similar error

Error:
Error-[SE] Syntax error
Following verilog source has syntax error :
“/vobs/asic_adc_dac_testchip/hydra_t/SE/assertions/hydra_t_strobe_assertions.sv”,
89: token is ‘,’, column 80
(1, current_time = $time) |=> @(ev_data_delay) ($time - current_time +
1),$display($stime,"\t setup_hold_checker= %d ",($time - (current_time
+1))) >= (SETUP_TIME+HOLD_TIME);

4

In reply to venkatasubbarao:


(current_time = $time) |=> @(ev_data_delay) 
($time-current_time > (SETUP_TIME+HOLD_TIME, 
$display("\t **setup_hold_checker**= %d ",$time-current_time) );

Basically, 
(expression, $display(...)) 
Ben systemverilog.us