In reply to dave_59:
yes sir you are right i got following error i had tried that before as well ending up with similar error
Error:
Error-[SE] Syntax error
Following verilog source has syntax error :
“/vobs/asic_adc_dac_testchip/hydra_t/SE/assertions/hydra_t_strobe_assertions.sv”,
89: token is ‘,’, column 80
(1, current_time = $time) |=> @(ev_data_delay) ($time - current_time +
1),$display($stime,"\t setup_hold_checker= %d ",($time - (current_time
+1))) >= (SETUP_TIME+HOLD_TIME);