Can we randomize strings in systemverilog

SystemVerilog
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4

In reply to sharat:

Thanks for this Code. I have one question regarding the array declaration. Over here we have made some conditions upon the numbers which are unsigned themselves. So, do we need to specify
" unsigned ". Can we not just write -

rand byte str [];
constraint condition{str.size <= 50;
                     foreach(str[i])
                       str[i] inside {[65:90], [97:122]};}