Can we randomize strings in systemverilog ? for example the below code is giving me the following error :- class chk; rand string abc; endclass module pg; chk c1; initial begin c1=new(); c1.randomize(); $display("%s \n",c1.abc); $finish; end endmodule Error…

In reply to dhpant28 : No, we cannot randomize a string variable. Here is a workaround that I could come up with for generating random strings. class temp_c; rand byte unsigned temp[]; constraint str_len { temp.size() == 4; } // Length of the string constraint temp_str_ascii { forea…

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Can we randomize strings in systemverilog

SystemVerilog

dhpant28 June 28, 2016, 7:12am 3

In reply to sharat:

thanks got it :)