Can we check the toggling of the signal within two clock edges using assertions?

SystemVerilog
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1

If I write assertions using stable in order to check the value of a signal


property check;
@(posedge clk) a |-> $stable(b);
endproperty

In the above code it will check the sampled value of the b at current clock cycle and the previous clock cycle.
Suppose, if the value of the b in the previous clock cycle was 1 and it has gone to 0 and again it will come to 1 so that the sampled value of b at current clock cycle is also 1. Then in the above case value of b is not stable, can we check this using assertions?

2

In reply to Manoj J:

I think that can happen iff b depends on some other clock that is not synchronous to clock of a.

In that case we can check as following :
Assuming b changes on a clock clk_b and a depends on a clock clk_a :

property check;
// num_clock_of_b_in_one_clock_of_a is greatest integer function of T_clk_a/T_clk_b ;
@(posedge clk_a) a |-> @(posedge clk_b) b[*num_clock_of_b_in_one_clock_of_a];
endproperty

Above will check if after being a `true at clk_a, signal b is true for those many number of clk_b untill clk_a again becomes high.

That will serve your intention.

3

In reply to Manoj J:
$stable in a concurrent assertions is checking for sequential stability. If you are looking for glitch detection, you need a timing check or use a different tool.