Can we check the toggling of the signal within two clock edges using assertions?

In reply to Manoj J:

I think that can happen iff b depends on some other clock that is not synchronous to clock of a.

In that case we can check as following :
Assuming b changes on a clock clk_b and a depends on a clock clk_a :

property check;
// num_clock_of_b_in_one_clock_of_a is greatest integer function of T_clk_a/T_clk_b ;
@(posedge clk_a) a |-> @(posedge clk_b) b[*num_clock_of_b_in_one_clock_of_a];
endproperty

Above will check if after being a `true at clk_a, signal b is true for those many number of clk_b untill clk_a again becomes high.

That will serve your intention.