In reply to ianmurph:
Concurrent assertions are DISALLOWED in tasks or in classes because they are dynamically instanced. However immediate assertions are legal.
Since your assertion impact interface signals, your best bet is to put the concurrent assertions in the interface. However, there is a mechanism to emulate concurrent assertions in classes using tasks. I explain this in my paper Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books: * Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
- Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
- A Pragmatic Approach to VMM Adoption
http://SystemVerilog.us/vf/VMM/VMM_pdf_release070506.zip
http://SystemVerilog.us/vf/VMM/VMM_code_release_071806.tar
- Papers:
- Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy - Reflections on Users’ Experiences with SVA
Reflections on Users’ Experiences with SVA | Verification Horizons - March 2022 | Verification Academy - SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy - SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/