Can I pass a local variable to an assertion (not seq or prop)?

SystemVerilog
,
1

Based on my reading and failed attempts I’m assuming the answer is no. Please correct me if I’m wrong.

2

In reply to mchal9thou:

Your question is ambiguous. What are you attempting to do?

3

In reply to ben@SystemVerilog.us:

I want to use a local variable in a property to keep track of the count in a multi-slot TDM frame, then pass the value of the local variable to its calling assertion for use in the print statements. Something like:

property slot_count_prop(slot_cnt);
always @(posedege) disable if (rst ==! 1)
(match, slot_cnt = slot_cnt + 1) |-> a & b;
endproperty

assert property (slot_count_prop(slot_cnt))
else
`uvm_error(“MATCH”, $sformatf(“a = %0b, b = %0b incorrect at slot %0d”, $sampled(a), $sampled(b), $sampled(slot_cnt)))

4

I want to use a local variable in a property to keep track of the count in a multi-slot TDM frame, then pass the value of the local variable to its calling assertion for use in the print statements.

You’ll need a function call with side effects to do this. Thus,

int slot_cnt; 
bit a, b; 
function void inc_slot_cnt(); 
  slot_cnt=slot_cnt + 1'b1; 
endfunction : inc_slot_cnt 
property slot_count_prop(slot_cnt);
  @(posedege) disable iff (rst ==! 1)
  (match, inc_slot_cnt()) |-> a && b; // the inc is evaluated in the Observed region
endproperty  // 
// See 1800 Table 11-1—Operators and data types
// Use the && || Binary logical operators for logical operations
// instead of the & | ^  Binary bitwise operators

assert property (slot_count_prop(slot_cnt)) // the slot_cnt used is from the Preponed region 
  else // the action block evaluated in the Reactive region
  `uvm_error("MATCH", $sformatf("a = %0b, b = %0b incorrect at slot %0d", $sampled(a),   $sampled(b), $sampled(slot_cnt)))
// *** NOTE: If you want the incremented slot_cnt, don't use the $sampled.

From my SVA book

8.2.4 Use formal arguments only when reuse is intended
Not every property needs to be declared with formal arguments since many properties may never be reused or instantiated multiple times, and are always applicable to a specific module. Declaring formal arguments adds more code in the declaration and instantiation of those properties. However, if re-use of the sequences or properties is desired, then it is worth the effort. When grouping multiple related assertions, use checkers with formal arguments and let the properties and assertions within the checkers inherit the values from the formal checker’s arguments.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115