Can I instantiate a tlm analysis fifo inside tb top and connect it to a monitor's analysis port?

UVM
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 Is it possible to instantiate a tlm analysis fifo inside tb top.sv and connect to the monitor 's analysis port of an agent??

 I intend to use this tlm fifo's output to send data to a reference model which is an entity.........
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In reply to krunal.modi:

You should instantiate your reference model in your scoreboard. A VHDL design should not be a problem.

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In reply to chr_sue:

How can I have an entity/module inside scoreboard class in UVM?

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In reply to krunal.modi:

You can’t. A class is dynamic, but a module or entity is static.
Instantiate the VHDL reference model in top.sv, and hook it up the signals of the interface driven by the agent.