Hi,
I am new to this field.I want to create multi master single slave testcase for i2c protocol is that possible in system verilog? I have created 2 environment for this multi master…if possible please suggest me how it is?
You can create multiple masters and slaves by using only one environment. In environment you have to create multiple agents , in that according to number of master and slave you create master agents and slaves agents.
In reply to varunkdave:
You can create multiple masters and slaves by using only one environment. In environment you have to create multiple agents , in that according to number of master and slave you create master agents and slaves agents.
It is possible in uvm but how it is possible in system verilog please guide me.
In reply to swethasundararaj:
From your last response it seams you are not using the UVM. Then your question becomes too broad a topic to answer without being more specific about what your environment looks like.