Can I add Delay in System Verilog function?

SystemVerilog
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In reply to milinraijada:

This is explained in section 13.4.4 Background processes spawned by function calls of the IEEE 1800-2012 LRM. See Get your free copy of the IEEE 1800-2023 SystemVerilog LRM - Verification Horizons to get a free copy.

The motivation for this feature was to allow a class constructor (which is a function) to start a thread. In most methodologies, like the UVM, you would never use this feature.