Can I add Delay in System Verilog function?

SystemVerilog
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2

In reply to milinraijada:

Hi All,
I have seen somewhere like this
function abc
fork
#100 $display(“System Verilog”);
join_none
so is it allowed to have delay and why ? and another question from where can I get such information about System Verilog?
Thanks

If you want dealys, you need to call a task

function int f(bit a); 
    #1; // ILLEGAL!!!!
    return !a; 
  endfunction 
Function 'f' has illegal use of delay or synchronization
  The uses can be wait, delay, clocking block assign, fork-join and other task
  calls with delays

For info on SystemVerilog (spelled as ONE word), go to
http://standards.ieee.org/getieee/1800/download/1800-2012.pdf

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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