Blocking assignment for clock divider

SystemVerilog
,
5

In reply to bmorris:
I was thinking more of what real hardware does. Unless the methodologies changed, if you have designs clocked at derived clocks, you still want all the flops to be controlled by the faster clocks. There are some power considerations. The approaches I saw (that was many years ago) are as follows:

  • devices clocked with the master clock are actually clocked through 2 stages of NAND gates, and it is the delayed clocks that drives all the devices. Thus,
bit clk, clkn1, clk1, clkn2, clk2;
assign clkn= !clk;
assign clk1 = ! clkn;
always @(posedge clk1) A <= A + 1;
//
// For devices that use the clkdiv
assign clk2n=!(clk && clkdiv);
assign clk2 = !clk2n;
always @(posedge clk2) B<=A;
// Now, what is above is really at the gate level.  At the RTL,
// both of these would work.
always @(posedge clk) if (clkdiv) B<=A; // OK too
always @(posedge clk && clkdiv) B <= A;

You seemed to stress in your original post the need of derived clocks. What I was saying is that one has to be very careful in using derived clocks as actual clocks rather than as clock enables. For synthesis, one needs to use the styles that are compatible with the synthesis tools.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us