In reply to dave_59:
The above example shows very poor design practices because it utilizes derived clocks as clocks along with the master clock. This is an invitation to poor designs and problems. TOO MANY CLOCKS!!! Tricking the simulator does not help, sorry; GBGO !!!
Why not do something like what is done in good designs? below is my recommendations.
module top;
bit clk, clkdiv;
int A,B;
always #5 clk = !clk;
always @(posedge clk) clkdiv <= !clkdiv;
always @(posedge clk) A <= A + 1;
always @(posedge clk && clkdiv) B <= A; // gets the current, non-updated value of A
// BTW, this is how hardware works.
initial begin
$monitor($time,,A,,B);
#100 $finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115