In reply to svishnu:
I would not say that they create race conditions. What they do is remove the synchronization between the the edges that supposed to be synchronized. Try this code with and without the NBA in the clock divider.
module top;
bit clk, clkdiv;
int A,B;
always #5 clk = !clk;
always @(posedge clk) clkdiv <= !clkdiv; // should be blocking
always @(posedge clk) A <= A + 1;
always @(posedge clkdiv) B <= A; // gets the updated value of A
initial begin
$monitor($time,,A,,B);
#100 $finish;
end
endmodule
The rule should be if you want to keep clocks synchronous in an RTL description, do not use non-blocking assignment in the clock path. This applies to gated clocks as well as clock dividers.