Bit width from Array size

SystemVerilog
,
4

In reply to dave_59:

Hi Dave,
I wrote a program for this.

Input in array: = [1,0,1]
Output: 5
Explanation: (101) in base 2 = (5) in base 10


module tb;
  
  initial begin
    bit [2:0]ab;
    bit cd[3];
    cd = '{1,0,1};
    
    ab = {>> {cd}};
    $display ("Value of packed is %d",ab);
    	
  end
  
endmodule

I dont want to hard the bit widths and array values hence i used the above approach.