I am trying to define the bit width from the size of an dynamic array. It throws an compile error.Can anyone provide a workaround?
module tb;
class A;
rand bit a[];
rand int temp;
rand bit bb[temp:0];
constraint b {a.size() == temp;}
constraint c {a.size <5;}
endclass
A a1;
initial begin
a1 = new();
if (!a1.randomize ())
begin
$display ("Error");
end
a1.bb = {>> {a1.a}};
$display ("Value of packed is %d",a1.bb);
end
endmodule
Error-[TCF-CETE] Cannot evaluate the expression
testbench.sv, 13
"temp"
Cannot evaluate the expression in left dimension bound.
The expression must be compile time constant.
The range of an array must be bounded by constant expression.The dimension which is mentioned after the array name is unpacked, it represents the depth of the array not the width of the array.
SystemVerilog requires all packed array dimensions (bit west) to be fixed at compile time. We can’t provide a workaround without knowing more about what you plan to do with this data.
Input in array: = [1,0,1]
Output: 5
Explanation: (101) in base 2 = (5) in base 10
module tb;
initial begin
bit [2:0]ab;
bit cd[3];
cd = '{1,0,1};
ab = {>> {cd}};
$display ("Value of packed is %d",ab);
end
endmodule
I dont want to hard the bit widths and array values hence i used the above approach.
That still does not answer my question. What do you plan to do with the variable ab? SystemVerilog does not allow variable sized packed arrays. Why are you trying to convert a unpacked dynamic array to packed? See http://xyproblem.info