In reply to rag123:
SystemVerilog requires all packed array dimensions (bit west) to be fixed at compile time. We can’t provide a workaround without knowing more about what you plan to do with this data.
In reply to rag123:
SystemVerilog requires all packed array dimensions (bit west) to be fixed at compile time. We can’t provide a workaround without knowing more about what you plan to do with this data.