Bit conversion using streaming operator

SystemVerilog
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1

I am told to do bit conversion using streaming operator.
I have a packet of 20 bits in size from a module and it must be packed to 32 bits packet while going from the module(Not zero padding)
How can I solve this issue using streaming operator?

2

In reply to bachan21:

I don’t think i understand your question properly…

but based on my understanding

module dut_tb;
    typedef struct {
      bit [7:0] addr;
      bit [7:0] data;
    } packet_in;
    logic [31:0] combined_data; 
   initial begin
      packet_in p_in;
      p_in.addr = 10'hAB;
      p_in.data = 10'hCD;
   
     combined_data = { { >>{p_in.addr,p_in.data} }  };
     $display("data = %0h",combined_data);    
   end 
endmodule
3

In reply to bachan21:

I don’t understand your question either. Where are the extra 12 bits supposed to come from? Try explaining wha the code would like like without using the streaming operator.

4

In reply to dave_59:

Hi Dave,

I am getting 20 bits packet from sdi module and that packet will be used in aximm after converting to 32 bits. I want to implement this logic in my TB scoreboard.

Let me elaborate my scoreboard logic with 8 bits and 16 bit data(for the simplicity of briefing) instead of 20 and 32 bits data packets. I am storing the 8 bit value into an array and that will be converted into an array of 16 bit values.

Lets assume an array of 8 bits in hex.

A8 = '{'h05, 'h1a, 'h46, 'had, 'h19, 'ha9}

And 16 bit converted array after streaming will be

B16 = '{'h051a, 'h46ad, 'h19a9}

This is the way I want my logic to be, but with 20 bits and 32 bits instead of 8 and 16 bits respectively
How can put this into a systemverilog code