Bit conversion using streaming operator

SystemVerilog
,
2

In reply to bachan21:

I don’t think i understand your question properly…

but based on my understanding

module dut_tb;
    typedef struct {
      bit [7:0] addr;
      bit [7:0] data;
    } packet_in;
    logic [31:0] combined_data; 
   initial begin
      packet_in p_in;
      p_in.addr = 10'hAB;
      p_in.data = 10'hCD;
   
     combined_data = { { >>{p_in.addr,p_in.data} }  };
     $display("data = %0h",combined_data);    
   end 
endmodule