Binding of SVA module with FSM and getting 'enum' state variables as input

SystemVerilog
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Dear all,
I need your advice/comments about SV bind construct.

I wrote a small module having on SVA assertions to verify a simple FSM. SVA module for bind requires to have fsm state variable in properties. State variable is enum type, for example {enum {IDLE, START, NOT_READY, WAIT, SEND , END_TX} fsm_state;}

I bind sva module to DUT in test bench. SVA module requires fsm_state as an input, how to pass ‘enum’ type. I mean I am clear about standard data types in IOs but not getting clear what type ‘fsm_state’ must I declare in sva module, while declaring as input to SVA module.

Thanks for your time and best wishes,
Mirza

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In reply to mirzaaur:

You should always use a typedef when declaring a user defined type such as an enum. Then you need to put that typedef in a package to share it among other modules.

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In reply to dave_59:

Thanks a lot!