Binding Interface to internal DUT

UVM
, , ,
1

I want to get internal generated clocks from the design to use them as triggering events in driver and scoreboard so I made an interface in top and tried to connect these internal clocks from the dut to it and set this interface in uvm_db_config although, these clocks appears z during simulation I don’t know the reason, I need some help



interface internal_sig_if
 (
input logic tx_clk ,
input logic rx_clk 
 );
  
  
parameter PRESCALE = 6'd16 ;  

endinterface



module top ;

 bfm_if  dut_if();
 internal_sig_if  internal_if();
 

  SYS_TOP #(.PRESCALE(PRESCALE) , .PAR_TYP(PARITY_TYP) , .PAR_EN(PARITY_EN)) dut (.REF_CLK(dut_if.REF_CLK)  ,
               .UART_CLK(dut_if.UART_CLK),
               .RST(dut_if.RST)          ,
               .RX_IN(dut_if.RX_IN)      ,
               .TX_OUT(dut_if.TX_OUT)   );
 


 bind dut internal_sig_if  dut_if_int_sig (dut.TX_CLK ,  dut.RX_CLK);


initial begin 
  uvm_config_db #(virtual  bfm_if) :: set(null,"*","dut_vif",dut_if) ;
  
  uvm_config_db #(virtual internal_sig_if) :: set(null , "*" , "internal_if" , internal_if) ;  // BINDED INTERFACE FOR INTERNAL SIGNALS

end
2

In reply to Hassan Khaled:

You only need one instance of the interface internal_sig_if, created by the bind construct. Remove the explicit instance of internal_if. Then the set statement should look like

uvm_config_db #(virtual internal_sig_if) :: set(null , "*" , "internal_if" , dut. dut_if_int_sig) ;

You did not show where the dut module is instaicated; you may need to change that to the proper instance path.

3

In reply to dave_59:

Hi Dave,
Have 2 questions on related topic

(1) The 4th argument to set would be the hierarchical path for the implicit instance ( via bind ) of ‘dut_if_int_sig’ within the user instantce of ‘dut’, right ?

Eg: 
uvm_config_db #(virtual internal_sig_if) :: set(null , "*" , "internal_if" , top_tb.<hierarchy_of_dut_instance>.dut_if_int_sig ) ;

(2) Scope for bind construct :


    // Signals rda, rdb , clk are internal signals within designModule
     bind  designModule propertyModule  dpM( .pa(rda) ,.pb(rdb) , .pclk(dclk) );
    

 Is the above bind legal ? i.e Does bind have complete scope visibility into the bound module 'designModule' ? OR Are only input/output ports of designModule visible ?
4

In reply to ABD_91:

  1. They did not show how the dut was instantiated. They figured it out.
  2. All of the identifiers that follow the bind target are from the perspective of the bind target. So most likely their bind statement could have dropped the ‘dut.’
 bind dut internal_sig_if  dut_if_int_sig (TX_CLK ,  RX_CLK);

Your bind statement is a substitute for putting the instance directly in the target module

module designModule(input dclk);
bit rda,rdb;
propertyModule  dpM( .pa(rda) ,.pb(rdb) , .pclk(dclk) );
...