Binding Interface to internal DUT

UVM
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3

In reply to dave_59:

Hi Dave,
Have 2 questions on related topic

(1) The 4th argument to set would be the hierarchical path for the implicit instance ( via bind ) of ‘dut_if_int_sig’ within the user instantce of ‘dut’, right ?

Eg: 
uvm_config_db #(virtual internal_sig_if) :: set(null , "*" , "internal_if" , top_tb.<hierarchy_of_dut_instance>.dut_if_int_sig ) ;

(2) Scope for bind construct :


    // Signals rda, rdb , clk are internal signals within designModule
     bind  designModule propertyModule  dpM( .pa(rda) ,.pb(rdb) , .pclk(dclk) );
    

 Is the above bind legal ? i.e Does bind have complete scope visibility into the bound module 'designModule' ? OR Are only input/output ports of designModule visible ?