Binding Assertion module

SystemVerilog
,
1

Hello,

I have following scenario.

file1
module block();
endmodule

file2
module Design();
block b();
endmodule

file 3
program test();
endprogram

file4
module assertion();
endmodule

file 5
module top();
Design d();
// I want to bind assertion module here to my module block.
endmodule

how can i bind assertion module to my block module from top module?

2 
module top();
  Design d();
  // I want to bind assertion module here to my module block.
  bind block assertion instname();
endmodule

There are many examples of using bind for SystemVerilog assertions around.

3

In reply to dave_59:

Thanks. That works well. but I am having multiple instances of block module inside my Design module. and i want to bind with specific module. so I am using following.

module Top();
Design d();
bind block : b assertion instance name();
endmodule

above code ends with an error: b is not valid instance name for module block. b must be valid name. Kindly guide me.

4

Mangal,
You could try:


module Top();
Design d();
bind block : d.b assertion instance name();
endmodule

Or directly use:


module Top();
Design d();
bind d.b assertion instance name();
endmodule

We cover this in our SVA book, pp 168- See: http://verifnews.org/publications/books/ if you want to get hold of an Indian edition of this book.

Regards
Srini
http:/www.verifworks.com