Bind interface to the instance of RTL top

SystemVerilog
, ,
2

When you use the ‘bind’ construct, it will create an instance of the interface for you. You do not need to create an instance separately.

Here is a working example:


module fifo(input in_dut, output out_dut);
endmodule

module dut_top(
            input                    FPGA_CLK100M_P,
            input                    FPGA_CLK100M_N,
            input                    LOGIC_RESETn, // Active LOW !!!
            input                    CLOCK_PRESENT
);

wire fifo_in, fifo_out;

fifo u_TIFIFO (
    .in_dut(fifo_in),
    .out_dut(fifo_out)
);

endmodule

interface itf (
    output reg fifo_in,
    input fifo_out
);
endinterface

module tb(itf itf_inst);
endmodule

module top();

wire in,out;

dut_top dutInst ();
itf itfInstncTI (in, out);

bind fifo itf itf_inst(.fifo_in(in_dut),.fifo_out(out_dut)); // bind creates instance of interface inside DUT

tb tbInst (dutInst.u_TIFIFO.itf_inst); //  here TB drives all the interface signal

endmodule