Bind - design path

Hello,
I wrote a SystemVerilog Module with SVA properties inside. When the property fails, I write an error message. I used “bind” to attach this module to every instance of a specific entity in the design. When I gen error message from the module I wrote, I don’t know to which entity in the deign it refers to.
Is there a way to know that(either by the code or by the simulator)?
Thanks

In reply to shaygueta:

If you have

assert property (foo); // or
assert property (foo) else $error(message");

The fail message should include the bind scope.

hi,
found a solution:
$display(“%m”);
Thanks anyway

In reply to shaygueta:
It would be much better to use $error because most tools have mechanisms for sorting messages by severity, and can report end of test results pass/fail by looking for 0 error messages.