Bind assertions to specific instances of design using wild card

SystemVerilog
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1

I want bind abc_assert to all instances of DUT under system.x.y* hierarchy.

bind dut:system.x.y*.abc abc_assert U_abc (.*);

Please note I don’t want to find all instances of DUT but just under system.x.y* hierarchy

When I tried with this wild card * I am getting compilation errors. Is there any way to get this working ?

2

In reply to gaganusc:

unfortunately, Systemverilog does not allow wildcarding of instance names. You will have to generate your list with a script, or manually.

3

In reply to dave_59:
Thanks Dave!