Bidirectional constraint using implication operator

SystemVerilog
1

In the following code, if a== 1 then b==0, because of bi-direction if b == 0 then, my understanding is a should be 1. But output seems to be different.

class ex_sv;

rand bit a;
rand bit b;

constraint c {
   (a==1) -> (b==0);
 }
endclass



module ex_mod;

ex_sv h = new();

initial begin
for( int i = 0; i<10; i++ ) begin
 void'(h.randomize() with {b==0;});
 $display("ITER : %0d a = %0d b = %0d",i, h.a, h.b);
end
end

endmodule

xcelium> run
ITER : 0 a = 0 b = 0
ITER : 1 a = 0 b = 0
ITER : 2 a = 1 b = 0
ITER : 3 a = 0 b = 0
ITER : 4 a = 0 b = 0
ITER : 5 a = 1 b = 0
ITER : 6 a = 1 b = 0
ITER : 7 a = 0 b = 0
ITER : 8 a = 1 b = 0
ITER : 9 a = 1 b = 0
xmsim: *W,RNQUIE: Simulation is complete.

2

In reply to saravanan_mobi:

See question about constraints | Verification Academy

3

In reply to dave_59:

Hi Dave,

I am unable to understand it. Could you please expalin in detail

4

(a==1) → (b==0) means that if a is 1, b must be 0. If a is 0, b could be anything(1 or 0). Not vice versa. If b == 0, a could be 0 or 1. There’s no constraint on that. However, because of (a==1) → (b==0), if b == 1, a cannot be 1, because that’ll violate the constraint itself.

So if in your inline constraint you put “with {b==1;}” you’ll always see a = 0.