In reply to ben@SystemVerilog.us:
Hello Ben,
Thanks for the reply.
I would really appreciate it if you could give me a short example. For instance, let’s say one of my tests writes a few registers and then I want to check that, right after the next clock cycle where a certain signal is asserted, another signals is also asserted/deasserted. I would also like to have a timeout so if that the first signal is never asserted an error is thrown after a certain amount of time.
The way I can think of would be:
while ("valid signal" == 0) @(posedge Clk);
assert (mySignal == 1'b1) else $fatal("throw error");
I guess I could do the timeout with some fork/join. What I am more concerned about is how to access my IPs signals from within my SV class.
For the AXI interfaces I have written down a BFM inside a SV interface, as described here: https://www.doulos.com/downloads/events/DVCon_08_abstractBFM_final.pdf
Since all I need to do with the AXI interface is read/write read_burst/write_burst this is fine, as I never have to access an actual interface signal from my class, and I can always go through the BFM.
For the rest of my IPs signals, which are much more custom, I was planning on doing something similar. I created a new interface which groups all those custom signals together and wrote a class inside of it to be able to handle those signals. However I now see it might be tricky to perform all the asserts I want to while going through the BFM…
What do you recommend I do in this case? would it be better to just use a virtual interface and handle the custom interface directly from my class instread of using a BFM?
Thanks.