In reply to arquer:
A few comments and remarks. In my career, I have done many designs and verifications and wrote several books on methodologies and assertion languages.
Question: what is the best way to check DUT’s compliance to specs?
- UVM methodology: has adopted a methodology that requires a separate monitor (a class) that collects the response and compliance to the protocol and a checker (a class) that checks for correctness. The idea of UVM is to bring uniformity in the way things are done and organized, thus allowing any future modifications or changes to be more easily understood.
- Concurrent SVA in classes are not allowed. That means that with strict UVM, all assertions must be done in the checker classes. BTW, UVM does not disallow assertions in interfaces or in DUTs or modules and SystemVerilog checkers bound to the DUT.
- My take:
[list]
- Assertions are statements that properties are met.
- Concurrent SVA is just a shorthand language to simplify the writing of assertions. For complex requirements, use tasks. See my paper: PAPER: Understanding the SVA Engine + Simple alternate solutions - SystemVerilog - Verification Academy
Abstract: Understanding the engine behind SVA provides not only a better appreciation and limitations of SVA, but in some situations provide features that cannot be simply implemented with the current definition of SVA. This paper first explains, by example, how a relatively simple assertion example can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multithreading and exit of threads upon a condition, such as an error in the assertion. The paper then provides examples that use computational variables within threads; those variables can cause, in some cases, errors in SVA. The strictly emulation model with tasks solves this issue. - Since concurrent SVA is not allowed in classes, one can use assertions in interfaces. See my White paper: “Using SVA for scoreboarding and TB designs” http://systemverilog.us/papers/sva4scoreboarding.pdf
and a related issue at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
available in the verification-horizons October-2013-volume-9-issue-3
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and SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment
For transactions that are interactive, a high-level model of the DUT is needed. - I am not particularly fond of the UVM style of MONITOR for collection and checker for verification, except for rare conditions where a lot of data must be collected and analyzed such as image processing, or when a lot of analysis and calculations must be done (FFT?). For protocols type of verifications, I prefer that the checking is done in interfaces and/or in the SystemVerilog checker bound to the interface or DUT.
Right now the code to perform this test is a task within the DUT’s driver.
[/list] I don’t see a big issue here. The only thing though is that you are forced to use tasks instead of SVA, thus making the assertions less readable.
From what I have read I suspect the intended way is to have assertion properties/sequences external to the driver and then enable them or disable them accordingly. I don’t understand how this is supposed to work though… my test task is parametrizable to be able to parametrize the test stimulus, therefore, the DUT’s response will depend on those… Am I supposed to have assertions for each individual possible case? As far as I know, SV assertion properties/sequences are not parametrizable right?
Properties can have arguments. Since properties are written into interfaces/modules/checkers you can pass to the actuals of the arguments the parameters you need. From my paper “Using SVA for scoreboarding and TB designs” I show how you can copy into the interfaces the needed values (such as your parameters) into the interface to be used in the SVA properties.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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